Fault Tolerance Limits and Input Stimulus Selection using an Implemented FPGA-based Testing System
Vassios, Vasilios/ Pouros, Sotirios/ Papakostas, Dimitrios/ Παπακώστας, Δημήτριος/ Πούρος, Σωτήριος/ Βάσσιος, Βασίλειος
Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Vassios, Vasilios | el |
| dc.contributor.author | Pouros, Sotirios | el |
| dc.contributor.author | Papakostas, Dimitrios | el |
| dc.contributor.other | Παπακώστας, Δημήτριος | el |
| dc.contributor.other | Πούρος, Σωτήριος | el |
| dc.contributor.other | Βάσσιος, Βασίλειος | el |
| dc.date.accessioned | 2015-07-03T11:48:53Z | el |
| dc.date.accessioned | 2018-02-28T16:16:44Z | - |
| dc.date.available | 2015-07-03T11:48:53Z | el |
| dc.date.available | 2018-02-28T16:16:44Z | - |
| dc.date.issued | 2014-11 | el |
| dc.identifier | 10.4236/jcc.2014.213003 | el |
| dc.identifier.citation | Journal: Journal of Computer and Communications, vol.2, no.13, 2014 | el |
| dc.identifier.citation | Papakostas, D., Vassios, V. and Pouros, S. (2014). Fault Tolerance Limits and Input Stimulus Selection using an Implemented FPGA-based Testing System. Journal of Computer and Communications [online]. 2(13), pp.18-24. Διαθέσιμο σε: http://www.scirp.org/journal/PaperInformation.aspx?PaperID=51506 [Ανακτήθηκε 19 Ιουλίου 2015] | el |
| dc.identifier.citation | Electronics and Circuits Conference, Beijing, 2014 | el |
| dc.identifier.issn | 2327-5227 | el |
| dc.identifier.issn | 2327-5219 | el |
| dc.identifier.uri | http://195.251.240.227/jspui/handle/123456789/10049 | - |
| dc.description | Δημοσιεύσεις μελών--ΣΤΕΦ--Τμήμα Ηλεκτρονικών Μηχανικών,2014 | el |
| dc.description.abstract | In this paper, the selection of fault tolerance limits and input stimulus using an implemented adaptive FPGA-based testing system based on a method utilizing wavelet transformation of the current waveforms is presented. The testing scheme is innovative because it offers the ability of applying different input stimulus signals with respect to the requirements of the examined circuit. Moreover, the method used is simple, offers a single-point test measurement solution and may easily be adapted to test various other analog and mixed-signal systems. Experimental results are presented showing the advantages of the proposed testing scheme. | el |
| dc.language.iso | en | el |
| dc.publisher | SCIRP | el |
| dc.relation.isbasedon | 2nd Electronics and Circuits Conference | el |
| dc.rights | Attribution-NonCommercial-Share Alike 3.0 Greece | el |
| dc.rights | Αναφορά Δημιουργού-Μη Εμπορική Χρήση-Παρόμοια Διανομή 3.0 Ελλάδα | el |
| dc.source.uri | http://www.scirp.org/journal/jcc/ | el |
| dc.subject | Fault Detection | el |
| dc.subject | External Testing System | el |
| dc.title | Fault Tolerance Limits and Input Stimulus Selection using an Implemented FPGA-based Testing System | el |
| dc.type | Article | el |
| heal.type | other | el |
| heal.type.en | Other | en |
| heal.dateAvailable | 2018-02-28T16:17:44Z | - |
| heal.language | el | el |
| heal.access | free | el |
| heal.recordProvider | ΤΕΙ Θεσσαλονίκης | el |
| heal.fullTextAvailability | false | el |
| heal.type.el | Άλλο | el |
| Appears in Collections: | Δημοσιεύσεις σε Περιοδικά | |
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