Ολοκληρωμένο περιβάλλον ανάπτυξης Ladder για PLC με τον ATmega32 (Bachelor thesis)

Κοκτσίδης, Ευθύμιος


Ladder is a programming language that graphically represents circuit diagrams of relay-logic hardware. It is used in the development of PLC (Programmable Logic Controller) S/W and its structure resembles that of electrical drawings. To date, Ladder is exclusively used in PLC, while its programming is implemented by IDE (Integrated Development Environment) which are mainly traded by the same companies that trade PLC. The present dissertation aims to build an IDE that enables the development of Ladder and its compiling to a code, which is functional and totally compatible with the ATmega32 MCU of ATMEL. The IDE is written in Visual C# and runs on Windows. Its main body is a 2- dimension list (x-axis for components, y-axis for rungs), which contains all the essential information for the depiction of the Ladder and the compiling that follows. The first step is to design the Ladder, taking into consideration both the ground rules of Ladder and the H/W limitations of the MCU. While drawing Ladder, users can add, remove or move the rungs, the parallel branches and the components (such as contacts and coils). The foresaid are realized in a graphical way using appropriate functions and auxiliary variables. Lastly, the compiling is accomplished by scanning the 2-D list for nodes and components using appropriate recursive algorithms. The only limitation is the MCU's specifications, that is its memory size, its clock frequency, its number of I/O pins and its peripherals (e.g. the timers). The results, though, were satisfying. The compiled code works as expected and its size, for a demo program consisting of six rungs, is around 500B.
Institution and School/Department of submitter: Σχολή Τεχνολογικών Εφαρμογών/ Τμήμα Μηχανικών Αυτοματισμού Τ.Ε.
Subject classification: Προγραμματιζόμενοι ελεγκτές
Programmable controllers
Atmel AVR μικροελεγκτής
Atmel AVR microcontroller
Γλώσσες προγραμματισμού (Ηλεκτρονικοί υπολογιστές)
Programming languages (Electronic computers)
Keywords: βιομηχανία;industry;PLC;προγραμματιζόμενος λογικός ελεγκτής;programmable logic controller;πρόγραμμα ανάπτυξης;development program;Ladder;ATmega32;IDE (Integrated Development Environment);μεταγλωττιστής;compiler;ATMEL
Description: Πτυχιακή εργασία - Σχολή Τεχνολογικών Εφαρμογών - Τμήμα Μηχανικών Αυτοματισμού, 2016 (α/α 8275)
URI: http://195.251.240.227/jspui/handle/123456789/13077
Item type: bachelorThesis
General Description / Additional Comments: Πτυχιακή εργασία
Subject classification: Προγραμματιζόμενοι ελεγκτές
Programmable controllers
Atmel AVR μικροελεγκτής
Atmel AVR microcontroller
Γλώσσες προγραμματισμού (Ηλεκτρονικοί υπολογιστές)
Programming languages (Electronic computers)
Item language: el
Item access scheme: account
Institution and School/Department of submitter: Σχολή Τεχνολογικών Εφαρμογών/ Τμήμα Μηχανικών Αυτοματισμού Τ.Ε.
Publication date: 2016-11-25
Bibliographic citation: Κοκτσίδης, Ε. (2016). Ολοκληρωμένο περιβάλλον ανάπτυξης Ladder για PLC με τον ATmega32 (Πτυχιακή εργασία). Αλεξάνδρειο ΤΕΙ Θεσσαλονίκης.
Abstract: Ladder is a programming language that graphically represents circuit diagrams of relay-logic hardware. It is used in the development of PLC (Programmable Logic Controller) S/W and its structure resembles that of electrical drawings. To date, Ladder is exclusively used in PLC, while its programming is implemented by IDE (Integrated Development Environment) which are mainly traded by the same companies that trade PLC. The present dissertation aims to build an IDE that enables the development of Ladder and its compiling to a code, which is functional and totally compatible with the ATmega32 MCU of ATMEL. The IDE is written in Visual C# and runs on Windows. Its main body is a 2- dimension list (x-axis for components, y-axis for rungs), which contains all the essential information for the depiction of the Ladder and the compiling that follows. The first step is to design the Ladder, taking into consideration both the ground rules of Ladder and the H/W limitations of the MCU. While drawing Ladder, users can add, remove or move the rungs, the parallel branches and the components (such as contacts and coils). The foresaid are realized in a graphical way using appropriate functions and auxiliary variables. Lastly, the compiling is accomplished by scanning the 2-D list for nodes and components using appropriate recursive algorithms. The only limitation is the MCU's specifications, that is its memory size, its clock frequency, its number of I/O pins and its peripherals (e.g. the timers). The results, though, were satisfying. The compiled code works as expected and its size, for a demo program consisting of six rungs, is around 500B.
Advisor name: Νικολαΐδης, Νικόλαος
Examining committee: Νικολαΐδης, Νικόλαος
Publishing department/division: Σχολή Τεχνολογικών Εφαρμογών/ Τμήμα Μηχανικών Αυτοματισμού
Publishing institution: teithe
Number of pages: σ. 65
Appears in Collections:Πτυχιακές Εργασίες

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